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[PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions
From: |
Alistair Francis |
Subject: |
[PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions |
Date: |
Wed, 14 Jun 2023 11:19:57 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Support disas for Zcmt* instructions only when related extensions
are supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index f2dd5fd531..6659f92179 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2505,7 +2505,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
op = rv_op_c_sqsp;
} else {
op = rv_op_c_fsdsp;
- if (((inst >> 12) & 0b01)) {
+ if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
switch ((inst >> 8) & 0b01111) {
case 8:
if (((inst >> 4) & 0b01111) >= 4) {
@@ -2531,6 +2531,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
} else {
switch ((inst >> 10) & 0b011) {
case 0:
+ if (!dec->cfg->ext_zcmt) {
+ break;
+ }
if (((inst >> 2) & 0xFF) >= 32) {
op = rv_op_cm_jalt;
} else {
@@ -2538,6 +2541,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 3:
+ if (!dec->cfg->ext_zcmp) {
+ break;
+ }
switch ((inst >> 5) & 0b011) {
case 1: op = rv_op_cm_mvsa01; break;
case 3: op = rv_op_cm_mva01s; break;
--
2.40.1
- [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size, (continued)
- [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size, Alistair Francis, 2023/06/13
- [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs, Alistair Francis, 2023/06/13
- [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address, Alistair Francis, 2023/06/13
- [PULL 34/60] target/riscv: smstateen check for fcsr, Alistair Francis, 2023/06/13
- [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info, Alistair Francis, 2023/06/13
- [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes, Alistair Francis, 2023/06/13
- [PULL 36/60] target/riscv: smstateen knobs, Alistair Francis, 2023/06/13
- [PULL 37/60] disas: Change type of disassemble_info.target_info to pointer, Alistair Francis, 2023/06/13
- [PULL 35/60] target/riscv: Reuse tb->flags.FS, Alistair Francis, 2023/06/13
- [PULL 38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h, Alistair Francis, 2023/06/13
- [PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions,
Alistair Francis <=
- [PULL 43/60] disas/riscv.c: Fix lines with over 80 characters, Alistair Francis, 2023/06/13
- [PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions, Alistair Francis, 2023/06/13
- [PULL 42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions, Alistair Francis, 2023/06/13
- [PULL 45/60] target/riscv: Fix target address to update badaddr, Alistair Francis, 2023/06/13
- [PULL 44/60] disas/riscv.c: Remove redundant parentheses, Alistair Francis, 2023/06/13
- [PULL 46/60] target/riscv: Introduce cur_insn_len into DisasContext, Alistair Francis, 2023/06/13
- [PULL 47/60] target/riscv: Change gen_goto_tb to work on displacements, Alistair Francis, 2023/06/13
- [PULL 50/60] target/riscv: Enable PC-relative translation, Alistair Francis, 2023/06/13
- [PULL 52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none", Alistair Francis, 2023/06/13
- [PULL 53/60] riscv/virt: Support using pflash via -blockdev option, Alistair Francis, 2023/06/13