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[PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_writ
From: |
Alistair Francis |
Subject: |
[PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write |
Date: |
Wed, 14 Jun 2023 11:19:41 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Use pmp_update_rule_addr() and pmp_update_rule_nums() separately to
update rule nums only once for each pmpcfg_csr_write. Then remove
pmp_update_rule() since it become unused.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-12-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 3c12690565..37e9985d6a 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -29,7 +29,6 @@
static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
uint8_t val);
static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
-static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
/*
* Accessor method to extract address matching type 'a field' from cfg reg
@@ -121,7 +120,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t
pmp_index, uint8_t val)
qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
} else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) {
env->pmp_state.pmp[pmp_index].cfg_reg = val;
- pmp_update_rule(env, pmp_index);
+ pmp_update_rule_addr(env, pmp_index);
return true;
}
} else {
@@ -209,18 +208,6 @@ void pmp_update_rule_nums(CPURISCVState *env)
}
}
-/*
- * Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
- * end address values.
- * This function is called relatively infrequently whereas the check that
- * an address is within a pmp rule is called often, so optimise that one
- */
-static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
-{
- pmp_update_rule_addr(env, pmp_index);
- pmp_update_rule_nums(env);
-}
-
static int pmp_is_in_range(CPURISCVState *env, int pmp_index,
target_ulong addr)
{
@@ -481,6 +468,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t
reg_index,
/* If PMP permission of any addr has been changed, flush TLB pages. */
if (modified) {
+ pmp_update_rule_nums(env);
tlb_flush(env_cpu(env));
}
}
--
2.40.1
- [PULL 14/60] target/riscv: Update pmp_get_tlb_size(), (continued)
- [PULL 14/60] target/riscv: Update pmp_get_tlb_size(), Alistair Francis, 2023/06/13
- [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Alistair Francis, 2023/06/13
- [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs, Alistair Francis, 2023/06/13
- [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed, Alistair Francis, 2023/06/13
- [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write(), Alistair Francis, 2023/06/13
- [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled, Alistair Francis, 2023/06/13
- [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Alistair Francis, 2023/06/13
- [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(), Alistair Francis, 2023/06/13
- [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated, Alistair Francis, 2023/06/13
- [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Alistair Francis, 2023/06/13
- [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write,
Alistair Francis <=
- [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry, Alistair Francis, 2023/06/13
- [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions, Alistair Francis, 2023/06/13
- [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro, Alistair Francis, 2023/06/13
- [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition, Alistair Francis, 2023/06/13
- [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition, Alistair Francis, 2023/06/13
- [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size, Alistair Francis, 2023/06/13
- [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs, Alistair Francis, 2023/06/13
- [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address, Alistair Francis, 2023/06/13
- [PULL 34/60] target/riscv: smstateen check for fcsr, Alistair Francis, 2023/06/13
- [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info, Alistair Francis, 2023/06/13