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[PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical
From: |
Alistair Francis |
Subject: |
[PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp |
Date: |
Wed, 14 Jun 2023 11:19:32 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
pmp_get_tlb_size can be separated from get_physical_address_pmp and is only
needed when ret == TRANSLATE_SUCCESS.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 065b433b88..52d0b043df 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -688,14 +688,11 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong
newpriv)
*
* @env: CPURISCVState
* @prot: The returned protection attributes
- * @tlb_size: TLB page size containing addr. It could be modified after PMP
- * permission checking. NULL if not set TLB page for addr.
* @addr: The physical address to be checked permission
* @access_type: The type of MMU access
* @mode: Indicates current privilege level.
*/
-static int get_physical_address_pmp(CPURISCVState *env, int *prot,
- target_ulong *tlb_size, hwaddr addr,
+static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
int size, MMUAccessType access_type,
int mode)
{
@@ -715,9 +712,6 @@ static int get_physical_address_pmp(CPURISCVState *env, int
*prot,
}
*prot = pmp_priv_to_page_prot(pmp_priv);
- if (tlb_size != NULL) {
- *tlb_size = pmp_get_tlb_size(env, addr);
- }
return TRANSLATE_SUCCESS;
}
@@ -906,7 +900,7 @@ restart:
}
int pmp_prot;
- int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+ int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
sizeof(target_ulong),
MMU_DATA_LOAD, PRV_S);
if (pmp_ret != TRANSLATE_SUCCESS) {
@@ -1302,8 +1296,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
prot &= prot2;
if (ret == TRANSLATE_SUCCESS) {
- ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+ ret = get_physical_address_pmp(env, &prot_pmp, pa,
size, access_type, mode);
+ tlb_size = pmp_get_tlb_size(env, pa);
qemu_log_mask(CPU_LOG_MMU,
"%s PMP address=" HWADDR_FMT_plx " ret %d prot"
@@ -1335,8 +1330,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
__func__, address, ret, pa, prot);
if (ret == TRANSLATE_SUCCESS) {
- ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+ ret = get_physical_address_pmp(env, &prot_pmp, pa,
size, access_type, mode);
+ tlb_size = pmp_get_tlb_size(env, pa);
qemu_log_mask(CPU_LOG_MMU,
"%s PMP address=" HWADDR_FMT_plx " ret %d prot"
--
2.40.1
- [PULL 05/60] target/riscv/cpu.c: remove set_priv_version(), (continued)
- [PULL 05/60] target/riscv/cpu.c: remove set_priv_version(), Alistair Francis, 2023/06/13
- [PULL 06/60] target/riscv: add PRIV_VERSION_LATEST, Alistair Francis, 2023/06/13
- [PULL 07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version, Alistair Francis, 2023/06/13
- [PULL 08/60] target/riscv: Update check for Zca/Zcf/Zcd, Alistair Francis, 2023/06/13
- [PULL 09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers, Alistair Francis, 2023/06/13
- [PULL 10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl(), Alistair Francis, 2023/06/13
- [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init(), Alistair Francis, 2023/06/13
- [PULL 12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init(), Alistair Francis, 2023/06/13
- [PULL 13/60] target/riscv: rework write_misa(), Alistair Francis, 2023/06/13
- [PULL 14/60] target/riscv: Update pmp_get_tlb_size(), Alistair Francis, 2023/06/13
- [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp,
Alistair Francis <=
- [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs, Alistair Francis, 2023/06/13
- [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed, Alistair Francis, 2023/06/13
- [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write(), Alistair Francis, 2023/06/13
- [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled, Alistair Francis, 2023/06/13
- [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Alistair Francis, 2023/06/13
- [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(), Alistair Francis, 2023/06/13
- [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated, Alistair Francis, 2023/06/13
- [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Alistair Francis, 2023/06/13
- [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Alistair Francis, 2023/06/13
- [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry, Alistair Francis, 2023/06/13