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[PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext
From: |
Alistair Francis |
Subject: |
[PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext |
Date: |
Wed, 14 Jun 2023 11:20:08 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
pc_succ_insn is no longer useful after the introduce of cur_insn_len
and all pc related value use diff value instead of absolute value.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index bd2da9b079..8a33da811e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -59,8 +59,6 @@ typedef enum {
typedef struct DisasContext {
DisasContextBase base;
- /* pc_succ_insn points to the instruction following base.pc_next */
- target_ulong pc_succ_insn;
target_ulong cur_insn_len;
target_ulong pc_save;
target_ulong priv_ver;
@@ -1149,7 +1147,6 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
/* Check for compressed insn */
if (ctx->cur_insn_len == 2) {
ctx->opcode = opcode;
- ctx->pc_succ_insn = ctx->base.pc_next + 2;
/*
* The Zca extension is added as way to refer to instructions in the C
* extension that do not include the floating-point loads and stores
@@ -1164,7 +1161,6 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
translator_lduw(env, &ctx->base,
ctx->base.pc_next + 2));
ctx->opcode = opcode32;
- ctx->pc_succ_insn = ctx->base.pc_next + 4;
for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
if (decoders[i].guard_func(ctx) &&
@@ -1185,7 +1181,6 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
uint32_t tb_flags = ctx->base.tb->flags;
ctx->pc_save = ctx->base.pc_first;
- ctx->pc_succ_insn = ctx->base.pc_first;
ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
@@ -1238,7 +1233,7 @@ static void riscv_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
ctx->ol = ctx->xl;
decode_opc(env, ctx, opcode16);
- ctx->base.pc_next = ctx->pc_succ_insn;
+ ctx->base.pc_next += ctx->cur_insn_len;
/* Only the first insn within a TB is allowed to cross a page boundary. */
if (ctx->base.is_jmp == DISAS_NEXT) {
--
2.40.1
- [PULL 50/60] target/riscv: Enable PC-relative translation, (continued)
- [PULL 50/60] target/riscv: Enable PC-relative translation, Alistair Francis, 2023/06/13
- [PULL 52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none", Alistair Francis, 2023/06/13
- [PULL 53/60] riscv/virt: Support using pflash via -blockdev option, Alistair Francis, 2023/06/13
- [PULL 55/60] util/log: Add vector registers to log, Alistair Francis, 2023/06/13
- [PULL 56/60] target/riscv: Fix initialized value for cur_pmmask, Alistair Francis, 2023/06/13
- [PULL 54/60] docs/system: riscv: Add pflash usage details, Alistair Francis, 2023/06/13
- [PULL 48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc, Alistair Francis, 2023/06/13
- [PULL 49/60] target/riscv: Use true diff for gen_pc_plus_diff, Alistair Francis, 2023/06/13
- [PULL 58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements, Alistair Francis, 2023/06/13
- [PULL 59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP, Alistair Francis, 2023/06/13
- [PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext,
Alistair Francis <=
- [PULL 57/60] target/riscv/vector_helper.c: clean up reference of MTYPE, Alistair Francis, 2023/06/13
- [PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only., Alistair Francis, 2023/06/13
- Re: [PULL 00/60] riscv-to-apply queue, Richard Henderson, 2023/06/14
- Re: [PULL 00/60] riscv-to-apply queue, Michael Tokarev, 2023/06/14