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[PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcf
From: |
Alistair Francis |
Subject: |
[PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. |
Date: |
Wed, 14 Jun 2023 11:20:17 +1000 |
From: Tommy Wu <tommy.wu@sifive.com>
According to the `The RISC-V Advanced Interrupt Architecture`
document, if register `mmsiaddrcfgh` of the domain has bit L set
to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-Id: <20230609055936.3925438-1-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_aplic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index afc5b54dbb..4bdc6a5d1a 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -688,13 +688,13 @@ static void riscv_aplic_write(void *opaque, hwaddr addr,
uint64_t value,
* domains).
*/
if (aplic->num_children &&
- !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+ !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
aplic->smsicfgaddr = value;
}
} else if (aplic->mmode && aplic->msimode &&
(addr == APLIC_SMSICFGADDRH)) {
if (aplic->num_children &&
- !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+ !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
}
} else if ((APLIC_SETIP_BASE <= addr) &&
--
2.40.1
- [PULL 53/60] riscv/virt: Support using pflash via -blockdev option, (continued)
- [PULL 53/60] riscv/virt: Support using pflash via -blockdev option, Alistair Francis, 2023/06/13
- [PULL 55/60] util/log: Add vector registers to log, Alistair Francis, 2023/06/13
- [PULL 56/60] target/riscv: Fix initialized value for cur_pmmask, Alistair Francis, 2023/06/13
- [PULL 54/60] docs/system: riscv: Add pflash usage details, Alistair Francis, 2023/06/13
- [PULL 48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc, Alistair Francis, 2023/06/13
- [PULL 49/60] target/riscv: Use true diff for gen_pc_plus_diff, Alistair Francis, 2023/06/13
- [PULL 58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements, Alistair Francis, 2023/06/13
- [PULL 59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP, Alistair Francis, 2023/06/13
- [PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext, Alistair Francis, 2023/06/13
- [PULL 57/60] target/riscv/vector_helper.c: clean up reference of MTYPE, Alistair Francis, 2023/06/13
- [PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.,
Alistair Francis <=
- Re: [PULL 00/60] riscv-to-apply queue, Richard Henderson, 2023/06/14
- Re: [PULL 00/60] riscv-to-apply queue, Michael Tokarev, 2023/06/14