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Re: [PULL 00/60] riscv-to-apply queue
From: |
Alistair Francis |
Subject: |
Re: [PULL 00/60] riscv-to-apply queue |
Date: |
Thu, 15 Jun 2023 14:03:44 +1000 |
On Wed, Jun 14, 2023 at 10:17 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> 14.06.2023 04:19, Alistair Francis wrote:
> > The following changes since commit fdd0df5340a8ebc8de88078387ebc85c5af7b40f:
> >
> > Merge tag 'pull-ppc-20230610' of https://gitlab.com/danielhb/qemu into
> > staging (2023-06-10 07:25:00 -0700)
> >
> > are available in the Git repository at:
> >
> > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230614
> >
> > for you to fetch changes up to 860029321d9ebdff47e89561de61e9441fead70a:
> >
> > hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are
> > read-only. (2023-06-14 10:04:30 +1000)
>
> Is anything there worth to apply to -stable?
>
> I picked this one:
> hw/riscv: qemu crash when NUMA nodes exceed available CPUs
Thanks for that!
>
> Anything else?
I don't think there is anything else, the other fixes are mostly for
experimental features, so I don't think we need to backport them.
Alistair
>
> Thanks!
>
> /mjt
>
> > Daniel Henrique Barboza (10):
> > target/riscv/vector_helper.c: skip set tail when vta is zero
> > target/riscv/cpu.c: add riscv_cpu_validate_v()
> > target/riscv/cpu.c: remove set_vext_version()
> > target/riscv/cpu.c: remove set_priv_version()
> > target/riscv: add PRIV_VERSION_LATEST
> > target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
> > target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
> > target/riscv/cpu.c: validate extensions before riscv_timer_init()
> > target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
> > target/riscv: rework write_misa()
> >
> > Himanshu Chauhan (1):
> > target/riscv: Smepmp: Return error when access permission not
> > allowed in PMP
> >
> > Ivan Klokov (1):
> > util/log: Add vector registers to log
> >
> > Mayuresh Chitale (3):
> > target/riscv: smstateen check for fcsr
> > target/riscv: Reuse tb->flags.FS
> > target/riscv: smstateen knobs
> >
> > Philippe Mathieu-Daudé (5):
> > hw/riscv/opentitan: Rename machine_[class]_init() functions
> > hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
> > hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
> > hw/riscv/opentitan: Explicit machine type definition
> > hw/riscv/opentitan: Correct OpenTitanState parent type/size
> >
> > Sunil V L (3):
> > hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
> > riscv/virt: Support using pflash via -blockdev option
> > docs/system: riscv: Add pflash usage details
> >
> > Tommy Wu (1):
> > hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are
> > read-only.
> >
> > Weiwei Li (33):
> > target/riscv: Move zc* out of the experimental properties
> > target/riscv: Mask the implicitly enabled extensions in isa_string
> > based on priv version
> > target/riscv: Update check for Zca/Zcf/Zcd
> > target/riscv: Update pmp_get_tlb_size()
> > target/riscv: Move pmp_get_tlb_size apart from
> > get_physical_address_pmp
> > target/riscv: Make the short cut really work in pmp_hart_has_privs
> > target/riscv: Change the return type of pmp_hart_has_privs() to bool
> > target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is
> > enabled
> > target/riscv: Remove unused paramters in pmp_hart_has_privs_default()
> > target/riscv: Flush TLB when MMWP or MML bits are changed
> > target/riscv: Update the next rule addr in pmpaddr_csr_write()
> > target/riscv: Flush TLB when pmpaddr is updated
> > target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
> > target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
> > target/riscv: Deny access if access is partially inside the PMP entry
> > target/riscv: Fix pointer mask transformation for vector address
> > target/riscv: Update cur_pmmask/base when xl changes
> > disas: Change type of disassemble_info.target_info to pointer
> > target/riscv: Split RISCVCPUConfig declarations from cpu.h into
> > cpu_cfg.h
> > target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
> > disas/riscv.c: Support disas for Zcm* extensions
> > disas/riscv.c: Support disas for Z*inx extensions
> > disas/riscv.c: Remove unused decomp_rv32/64 value for vector
> > instructions
> > disas/riscv.c: Fix lines with over 80 characters
> > disas/riscv.c: Remove redundant parentheses
> > target/riscv: Fix target address to update badaddr
> > target/riscv: Introduce cur_insn_len into DisasContext
> > target/riscv: Change gen_goto_tb to work on displacements
> > target/riscv: Change gen_set_pc_imm to gen_update_pc
> > target/riscv: Use true diff for gen_pc_plus_diff
> > target/riscv: Enable PC-relative translation
> > target/riscv: Remove pc_succ_insn from DisasContext
> > target/riscv: Fix initialized value for cur_pmmask
> >
> > Xiao Wang (2):
> > target/riscv/vector_helper.c: clean up reference of MTYPE
> > target/riscv/vector_helper.c: Remove the check for extra tail
> > elements
> >
> > Yin Wang (1):
> > hw/riscv: qemu crash when NUMA nodes exceed available CPUs
> >
> > docs/system/riscv/virt.rst | 31 +
> > include/disas/dis-asm.h | 2 +-
> > include/hw/core/cpu.h | 2 +
> > include/hw/riscv/opentitan.h | 6 +-
> > include/qemu/log.h | 1 +
> > target/riscv/cpu.h | 117 +--
> > target/riscv/cpu_cfg.h | 136 +++
> > target/riscv/pmp.h | 11 +-
> > accel/tcg/cpu-exec.c | 3 +
> > disas/riscv.c | 1194
> > +++++++++++++-----------
> > hw/intc/riscv_aplic.c | 4 +-
> > hw/riscv/numa.c | 6 +
> > hw/riscv/opentitan.c | 38 +-
> > hw/riscv/virt.c | 59 +-
> > target/riscv/cpu.c | 384 +++++---
> > target/riscv/cpu_helper.c | 37 +-
> > target/riscv/csr.c | 75 +-
> > target/riscv/pmp.c | 205 ++--
> > target/riscv/translate.c | 99 +-
> > target/riscv/vector_helper.c | 33 +-
> > util/log.c | 2 +
> > target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
> > target/riscv/insn_trans/trans_rvd.c.inc | 12 +-
> > target/riscv/insn_trans/trans_rvf.c.inc | 21 +-
> > target/riscv/insn_trans/trans_rvi.c.inc | 46 +-
> > target/riscv/insn_trans/trans_rvv.c.inc | 4 +-
> > target/riscv/insn_trans/trans_rvzawrs.c.inc | 2 +-
> > target/riscv/insn_trans/trans_rvzce.c.inc | 10 +-
> > target/riscv/insn_trans/trans_xthead.c.inc | 2 +-
> > 29 files changed, 1442 insertions(+), 1102 deletions(-)
> > create mode 100644 target/riscv/cpu_cfg.h
> >
>
- [PULL 54/60] docs/system: riscv: Add pflash usage details, (continued)
- [PULL 54/60] docs/system: riscv: Add pflash usage details, Alistair Francis, 2023/06/13
- [PULL 48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc, Alistair Francis, 2023/06/13
- [PULL 49/60] target/riscv: Use true diff for gen_pc_plus_diff, Alistair Francis, 2023/06/13
- [PULL 58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements, Alistair Francis, 2023/06/13
- [PULL 59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP, Alistair Francis, 2023/06/13
- [PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext, Alistair Francis, 2023/06/13
- [PULL 57/60] target/riscv/vector_helper.c: clean up reference of MTYPE, Alistair Francis, 2023/06/13
- [PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only., Alistair Francis, 2023/06/13
- Re: [PULL 00/60] riscv-to-apply queue, Richard Henderson, 2023/06/14
- Re: [PULL 00/60] riscv-to-apply queue, Michael Tokarev, 2023/06/14
- Re: [PULL 00/60] riscv-to-apply queue,
Alistair Francis <=