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[PULL 03/26] target/arm: SCR_EL3.NS may be RES1
From: |
Peter Maydell |
Subject: |
[PULL 03/26] target/arm: SCR_EL3.NS may be RES1 |
Date: |
Fri, 23 Jun 2023 13:31:12 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
With RME, SEL2 must also be present to support secure state.
The NS bit is RES1 if SEL2 is not present.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2f0d9226ec..9132d4de6a4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1855,6 +1855,9 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
}
if (cpu_isar_feature(aa64_sel2, cpu)) {
valid_mask |= SCR_EEL2;
+ } else if (cpu_isar_feature(aa64_rme, cpu)) {
+ /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
+ value |= SCR_NS;
}
if (cpu_isar_feature(aa64_mte, cpu)) {
valid_mask |= SCR_ATA;
--
2.34.1
- [PULL 01/26] target/arm: Add isar_feature_aa64_rme, (continued)
- [PULL 01/26] target/arm: Add isar_feature_aa64_rme, Peter Maydell, 2023/06/23
- [PULL 02/26] target/arm: Update SCR and HCR for RME, Peter Maydell, 2023/06/23
- [PULL 06/26] include/exec/memattrs: Add two bits of space to MemTxAttrs, Peter Maydell, 2023/06/23
- [PULL 05/26] target/arm: Introduce ARMSecuritySpace, Peter Maydell, 2023/06/23
- [PULL 07/26] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx, Peter Maydell, 2023/06/23
- [PULL 08/26] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, Peter Maydell, 2023/06/23
- [PULL 09/26] target/arm: Remove __attribute__((nonnull)) from ptw.c, Peter Maydell, 2023/06/23
- [PULL 13/26] target/arm: Handle no-execute for Realm and Root regimes, Peter Maydell, 2023/06/23
- [PULL 12/26] target/arm: Handle Block and Page bits for security space, Peter Maydell, 2023/06/23
- [PULL 20/26] target/arm: Add cpu properties for enabling FEAT_RME, Peter Maydell, 2023/06/23
- [PULL 03/26] target/arm: SCR_EL3.NS may be RES1,
Peter Maydell <=
- [PULL 19/26] target/arm: Implement the granule protection check, Peter Maydell, 2023/06/23
- [PULL 04/26] target/arm: Add RME cpregs, Peter Maydell, 2023/06/23
- [PULL 11/26] target/arm: NSTable is RES0 for the RME EL3 regime, Peter Maydell, 2023/06/23
- [PULL 10/26] target/arm: Pipe ARMSecuritySpace through ptw.c, Peter Maydell, 2023/06/23
- [PULL 14/26] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate, Peter Maydell, 2023/06/23
- [PULL 16/26] target/arm: Use get_phys_addr_with_struct for stage2, Peter Maydell, 2023/06/23
- [PULL 15/26] target/arm: Move s1_is_el0 into S1Translate, Peter Maydell, 2023/06/23
- [PULL 17/26] target/arm: Add GPC syndrome, Peter Maydell, 2023/06/23
- [PULL 21/26] docs/system/arm: Document FEAT_RME, Peter Maydell, 2023/06/23
- [PULL 23/26] target/arm: Restructure has_vfp_d32 test, Peter Maydell, 2023/06/23