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[PULL 14/26] target/arm: Use get_phys_addr_with_struct in S1_ptw_transla
From: |
Peter Maydell |
Subject: |
[PULL 14/26] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate |
Date: |
Fri, 23 Jun 2023 13:31:23 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Do not provide a fast-path for physical addresses,
as those will need to be validated for GPC.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 44 +++++++++++++++++---------------------------
1 file changed, 17 insertions(+), 27 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 45271d666b3..6d5e4855a33 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -264,37 +264,27 @@ static bool S1_ptw_translate(CPUARMState *env,
S1Translate *ptw,
* From gdbstub, do not use softmmu so that we don't modify the
* state of the cpu at all, including softmmu tlb contents.
*/
- if (regime_is_stage2(s2_mmu_idx)) {
- S1Translate s2ptw = {
- .in_mmu_idx = s2_mmu_idx,
- .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
- .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
- .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
- : space == ARMSS_Realm ? ARMSS_Realm
- : ARMSS_NonSecure),
- .in_debug = true,
- };
- GetPhysAddrResult s2 = { };
+ S1Translate s2ptw = {
+ .in_mmu_idx = s2_mmu_idx,
+ .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
+ .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
+ .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
+ : space == ARMSS_Realm ? ARMSS_Realm
+ : ARMSS_NonSecure),
+ .in_debug = true,
+ };
+ GetPhysAddrResult s2 = { };
- if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
- false, &s2, fi)) {
- goto fail;
- }
- ptw->out_phys = s2.f.phys_addr;
- pte_attrs = s2.cacheattrs.attrs;
- ptw->out_secure = s2.f.attrs.secure;
- ptw->out_space = s2.f.attrs.space;
- } else {
- /* Regime is physical. */
- ptw->out_phys = addr;
- pte_attrs = 0;
- ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S;
- ptw->out_space = (s2_mmu_idx == ARMMMUIdx_Phys_S ? ARMSS_Secure
- : space == ARMSS_Realm ? ARMSS_Realm
- : ARMSS_NonSecure);
+ if (get_phys_addr_with_struct(env, &s2ptw, addr,
+ MMU_DATA_LOAD, &s2, fi)) {
+ goto fail;
}
+ ptw->out_phys = s2.f.phys_addr;
+ pte_attrs = s2.cacheattrs.attrs;
ptw->out_host = NULL;
ptw->out_rw = false;
+ ptw->out_secure = s2.f.attrs.secure;
+ ptw->out_space = s2.f.attrs.space;
} else {
#ifdef CONFIG_TCG
CPUTLBEntryFull *full;
--
2.34.1
- [PULL 08/26] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, (continued)
- [PULL 08/26] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, Peter Maydell, 2023/06/23
- [PULL 09/26] target/arm: Remove __attribute__((nonnull)) from ptw.c, Peter Maydell, 2023/06/23
- [PULL 13/26] target/arm: Handle no-execute for Realm and Root regimes, Peter Maydell, 2023/06/23
- [PULL 12/26] target/arm: Handle Block and Page bits for security space, Peter Maydell, 2023/06/23
- [PULL 20/26] target/arm: Add cpu properties for enabling FEAT_RME, Peter Maydell, 2023/06/23
- [PULL 03/26] target/arm: SCR_EL3.NS may be RES1, Peter Maydell, 2023/06/23
- [PULL 19/26] target/arm: Implement the granule protection check, Peter Maydell, 2023/06/23
- [PULL 04/26] target/arm: Add RME cpregs, Peter Maydell, 2023/06/23
- [PULL 11/26] target/arm: NSTable is RES0 for the RME EL3 regime, Peter Maydell, 2023/06/23
- [PULL 10/26] target/arm: Pipe ARMSecuritySpace through ptw.c, Peter Maydell, 2023/06/23
- [PULL 14/26] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate,
Peter Maydell <=
- [PULL 16/26] target/arm: Use get_phys_addr_with_struct for stage2, Peter Maydell, 2023/06/23
- [PULL 15/26] target/arm: Move s1_is_el0 into S1Translate, Peter Maydell, 2023/06/23
- [PULL 17/26] target/arm: Add GPC syndrome, Peter Maydell, 2023/06/23
- [PULL 21/26] docs/system/arm: Document FEAT_RME, Peter Maydell, 2023/06/23
- [PULL 23/26] target/arm: Restructure has_vfp_d32 test, Peter Maydell, 2023/06/23
- [PULL 18/26] target/arm: Implement GPC exceptions, Peter Maydell, 2023/06/23
- [PULL 24/26] hw/arm/sbsa-ref: add ITS support in SBSA GIC, Peter Maydell, 2023/06/23
- [PULL 22/26] host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang, Peter Maydell, 2023/06/23
- [PULL 26/26] pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym, Peter Maydell, 2023/06/23
- [PULL 25/26] target/arm: Fix sve predicate store, 8 <= VQ <= 15, Peter Maydell, 2023/06/23