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[PULL 15/26] target/arm: Move s1_is_el0 into S1Translate
From: |
Peter Maydell |
Subject: |
[PULL 15/26] target/arm: Move s1_is_el0 into S1Translate |
Date: |
Fri, 23 Jun 2023 13:31:24 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Instead of passing this to get_phys_addr_lpae, stash it
in the S1Translate structure.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 27 ++++++++++++---------------
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 6d5e4855a33..558b4b731b8 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -24,6 +24,12 @@ typedef struct S1Translate {
ARMSecuritySpace in_space;
bool in_secure;
bool in_debug;
+ /*
+ * If this is stage 2 of a stage 1+2 page table walk, then this must
+ * be true if stage 1 is an EL0 access; otherwise this is ignored.
+ * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}.
+ */
+ bool in_s1_is_el0;
bool out_secure;
bool out_rw;
bool out_be;
@@ -34,8 +40,7 @@ typedef struct S1Translate {
} S1Translate;
static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
- uint64_t address,
- MMUAccessType access_type, bool s1_is_el0,
+ uint64_t address, MMUAccessType access_type,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi);
static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
@@ -1289,17 +1294,12 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool
is_aa64, uint64_t tcr,
* @ptw: Current and next stage parameters for the walk.
* @address: virtual address to get physical address for
* @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
- * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
- * (so this is a stage 2 page table walk),
- * must be true if this is stage 2 of a stage 1+2
- * walk for an EL0 access. If @mmu_idx is anything else,
- * @s1_is_el0 is ignored.
* @result: set on translation success,
* @fi: set to fault info if the translation fails
*/
static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
uint64_t address,
- MMUAccessType access_type, bool s1_is_el0,
+ MMUAccessType access_type,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
@@ -1635,7 +1635,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
result->f.prot = get_S2prot_noexecute(ap);
} else {
xn = extract64(attrs, 53, 2);
- result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
+ result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0);
}
} else {
int nse, ns = extract32(attrs, 5, 1);
@@ -2858,7 +2858,6 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
bool ret, ipa_secure;
ARMCacheAttrs cacheattrs1;
ARMSecuritySpace ipa_space;
- bool is_el0;
uint64_t hcr;
ret = get_phys_addr_with_struct(env, ptw, address, access_type, result,
fi);
@@ -2872,7 +2871,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
ipa_secure = result->f.attrs.secure;
ipa_space = result->f.attrs.space;
- is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
+ ptw->in_s1_is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
ptw->in_secure = ipa_secure;
ptw->in_space = ipa_space;
@@ -2891,8 +2890,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
ret = get_phys_addr_pmsav8(env, ipa, access_type,
ptw->in_mmu_idx, is_secure, result, fi);
} else {
- ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
- is_el0, result, fi);
+ ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi);
}
fi->s2addr = ipa;
@@ -3078,8 +3076,7 @@ static bool get_phys_addr_with_struct(CPUARMState *env,
S1Translate *ptw,
}
if (regime_using_lpae_format(env, mmu_idx)) {
- return get_phys_addr_lpae(env, ptw, address, access_type, false,
- result, fi);
+ return get_phys_addr_lpae(env, ptw, address, access_type, result, fi);
} else if (arm_feature(env, ARM_FEATURE_V7) ||
regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, ptw, address, access_type, result, fi);
--
2.34.1
- [PULL 13/26] target/arm: Handle no-execute for Realm and Root regimes, (continued)
- [PULL 13/26] target/arm: Handle no-execute for Realm and Root regimes, Peter Maydell, 2023/06/23
- [PULL 12/26] target/arm: Handle Block and Page bits for security space, Peter Maydell, 2023/06/23
- [PULL 20/26] target/arm: Add cpu properties for enabling FEAT_RME, Peter Maydell, 2023/06/23
- [PULL 03/26] target/arm: SCR_EL3.NS may be RES1, Peter Maydell, 2023/06/23
- [PULL 19/26] target/arm: Implement the granule protection check, Peter Maydell, 2023/06/23
- [PULL 04/26] target/arm: Add RME cpregs, Peter Maydell, 2023/06/23
- [PULL 11/26] target/arm: NSTable is RES0 for the RME EL3 regime, Peter Maydell, 2023/06/23
- [PULL 10/26] target/arm: Pipe ARMSecuritySpace through ptw.c, Peter Maydell, 2023/06/23
- [PULL 14/26] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate, Peter Maydell, 2023/06/23
- [PULL 16/26] target/arm: Use get_phys_addr_with_struct for stage2, Peter Maydell, 2023/06/23
- [PULL 15/26] target/arm: Move s1_is_el0 into S1Translate,
Peter Maydell <=
- [PULL 17/26] target/arm: Add GPC syndrome, Peter Maydell, 2023/06/23
- [PULL 21/26] docs/system/arm: Document FEAT_RME, Peter Maydell, 2023/06/23
- [PULL 23/26] target/arm: Restructure has_vfp_d32 test, Peter Maydell, 2023/06/23
- [PULL 18/26] target/arm: Implement GPC exceptions, Peter Maydell, 2023/06/23
- [PULL 24/26] hw/arm/sbsa-ref: add ITS support in SBSA GIC, Peter Maydell, 2023/06/23
- [PULL 22/26] host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang, Peter Maydell, 2023/06/23
- [PULL 26/26] pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym, Peter Maydell, 2023/06/23
- [PULL 25/26] target/arm: Fix sve predicate store, 8 <= VQ <= 15, Peter Maydell, 2023/06/23
- Re: [PULL 00/26] target-arm queue, Richard Henderson, 2023/06/25