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[PULL 16/26] target/arm: Use get_phys_addr_with_struct for stage2
From: |
Peter Maydell |
Subject: |
[PULL 16/26] target/arm: Use get_phys_addr_with_struct for stage2 |
Date: |
Fri, 23 Jun 2023 13:31:25 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
This fixes a bug in which we failed to initialize
the result attributes properly after the memset.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 558b4b731b8..7c4526e2da1 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -39,10 +39,6 @@ typedef struct S1Translate {
void *out_host;
} S1Translate;
-static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
- uint64_t address, MMUAccessType access_type,
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi);
-
static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
target_ulong address,
MMUAccessType access_type,
@@ -2886,12 +2882,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
cacheattrs1 = result->cacheattrs;
memset(result, 0, sizeof(*result));
- if (arm_feature(env, ARM_FEATURE_PMSA)) {
- ret = get_phys_addr_pmsav8(env, ipa, access_type,
- ptw->in_mmu_idx, is_secure, result, fi);
- } else {
- ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi);
- }
+ ret = get_phys_addr_with_struct(env, ptw, ipa, access_type, result, fi);
fi->s2addr = ipa;
/* Combine the S1 and S2 perms. */
--
2.34.1
- [PULL 09/26] target/arm: Remove __attribute__((nonnull)) from ptw.c, (continued)
- [PULL 09/26] target/arm: Remove __attribute__((nonnull)) from ptw.c, Peter Maydell, 2023/06/23
- [PULL 13/26] target/arm: Handle no-execute for Realm and Root regimes, Peter Maydell, 2023/06/23
- [PULL 12/26] target/arm: Handle Block and Page bits for security space, Peter Maydell, 2023/06/23
- [PULL 20/26] target/arm: Add cpu properties for enabling FEAT_RME, Peter Maydell, 2023/06/23
- [PULL 03/26] target/arm: SCR_EL3.NS may be RES1, Peter Maydell, 2023/06/23
- [PULL 19/26] target/arm: Implement the granule protection check, Peter Maydell, 2023/06/23
- [PULL 04/26] target/arm: Add RME cpregs, Peter Maydell, 2023/06/23
- [PULL 11/26] target/arm: NSTable is RES0 for the RME EL3 regime, Peter Maydell, 2023/06/23
- [PULL 10/26] target/arm: Pipe ARMSecuritySpace through ptw.c, Peter Maydell, 2023/06/23
- [PULL 14/26] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate, Peter Maydell, 2023/06/23
- [PULL 16/26] target/arm: Use get_phys_addr_with_struct for stage2,
Peter Maydell <=
- [PULL 15/26] target/arm: Move s1_is_el0 into S1Translate, Peter Maydell, 2023/06/23
- [PULL 17/26] target/arm: Add GPC syndrome, Peter Maydell, 2023/06/23
- [PULL 21/26] docs/system/arm: Document FEAT_RME, Peter Maydell, 2023/06/23
- [PULL 23/26] target/arm: Restructure has_vfp_d32 test, Peter Maydell, 2023/06/23
- [PULL 18/26] target/arm: Implement GPC exceptions, Peter Maydell, 2023/06/23
- [PULL 24/26] hw/arm/sbsa-ref: add ITS support in SBSA GIC, Peter Maydell, 2023/06/23
- [PULL 22/26] host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang, Peter Maydell, 2023/06/23
- [PULL 26/26] pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym, Peter Maydell, 2023/06/23
- [PULL 25/26] target/arm: Fix sve predicate store, 8 <= VQ <= 15, Peter Maydell, 2023/06/23
- Re: [PULL 00/26] target-arm queue, Richard Henderson, 2023/06/25