Re: geda/lepton schematics

[karl]

Felix:
> On Fri, Mar 25, 2022 at 10:43:14PM +0100, karl@aspodata.se wrote:
...
> >  Would something like this suffice ?
> > 
> > $ lepton-netlist -g verilog arm_can_test.sch
> > [..]
> 
> What do you intend to do with it?

You wrote earlier that:
> Connections in gEDA schematics are implicit, and port positions are
> needed to infer them. For this, the symbol database is required. The gEDA
> library has been used to look up the symbols.

By running the lepton/geda netlister you get the connections.
You don't need to have your own code for it.

and:
> I think it is desirable to eventually have Qucs <=> Verilog <=> gGEDA
> roundtrips for schematics. (It doesn't have to be Verilog, but some
> suitable standardised format for circuit models.)

lepton/geda has some code to produce verilog.
If verilog is the if. you want, why spend time on the geda plugin when
it might be more fruitful to get help from e.g. the lepton people to
shape up their verilog handling ?

The drawback with that would be back annotation if I understand you:
> >  When you do (the old way) lepton-sch2pcb or gsch2pcb, you get a
> >  .net file.
> This is lossy. If you read it into Gnucap, you won't get your schematic
> back (nor a Qucs, Verilog or similar schematic). If you do something
> more elaborate (say parasitics extraction), how will you annotate the
> schematic with your findings?

There are some work done about back-annotation:
 https://archive.org/details/pcb-rnd-back-annotation

Could something like that be sufficient ?

Regards,
/Karl Hammar