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Re: geda/lepton schematics
From: |
karl |
Subject: |
Re: geda/lepton schematics |
Date: |
Mon, 28 Mar 2022 12:05:58 +0200 (CEST) |
Felix:
...
> A subsheet is essentially a subcircuit macro. It exists in spice
> (.subckt) and in Verilog ("module" with sub-components), and in the
> others as well.
>
> Such a macro has ports, internal nets, parameters and a list of
> components + the connectivity (!). Much the same as a schematic
> subsheet, just without the positions.
...
Soo,
every sym file is a module
every sch file is a module
you only need to find out the implicit nets within the sch file
not for the whole system
and you could basically make, as a cache, verilog files of every
sch/sym file you have, and later only update the subsheet references.
Hälsningar,
/Karl Hammar
-----------------------------------------------------------------------
Aspö Data
Lilla Aspö 148
S-742 94 Östhammar
Sverige
- Re: geda/lepton schematics, (continued)
- Re: geda/lepton schematics, karl, 2022/03/25
- Re: geda/lepton schematics, Felix Salfelder, 2022/03/25
- Re: geda/lepton schematics, Felix Salfelder, 2022/03/25
- Re: geda/lepton schematics, karl, 2022/03/26
- Re: geda/lepton schematics, Felix Salfelder, 2022/03/26
- Re: geda/lepton schematics, karl, 2022/03/26
- Re: geda/lepton schematics, Felix Salfelder, 2022/03/26
- Re: geda/lepton schematics, karl, 2022/03/27
- Re: geda/lepton schematics, karl, 2022/03/27
- Re: geda/lepton schematics, Felix Salfelder, 2022/03/27
- Re: geda/lepton schematics,
karl <=
- Re: geda/lepton schematics, Felix Salfelder, 2022/03/30
- Re: geda/lepton schematics, karl, 2022/03/30
- Re: geda/lepton schematics, Felix Salfelder, 2022/03/31
- Re: geda/lepton schematics, karl, 2022/03/31
- Re: geda/lepton schematics, Felix Salfelder, 2022/03/31
- Re: geda/lepton schematics, karl, 2022/03/31
- Re: geda/lepton schematics, al davis, 2022/03/27
- Re: geda/lepton schematics, karl, 2022/03/26
- Re: geda/lepton schematics, Felix Salfelder, 2022/03/26
- Re: geda/lepton schematics, al davis, 2022/03/25