Re: geda/lepton schematics

[karl]

Felix:
> On Mon, Mar 28, 2022 at 12:05:58PM +0200, karl@aspodata.se wrote:
> >  every sym file is a module
> >  every sch file is a module
> 
> gEDA uses one file for one schematic, and one file for one symbol.
> Perhaps it makes sense to stick with it.

Yes, I thought so.

> Verilog does not allow top level components, but the standard has a
> notion of "main". It looks C inspired, maybe it is.
>
> A schematic file could be stored in a verilog file that contains a
> single "main" module, and the main module contains the components (port
> values represent connectivity) and maybe text or graphics.

Seems "everything" is a module, and you can just call the top module
main if you'd like.

...
> >From there, you can think about flattening. Perhaps gnucap-geda does it
> "the wrong way", but it will adapt.

>From what I read about verilog-ams, you don't need to flatten the nets,
it follows from the structure.

Regards,
/Karl Hammar