Re: geda/lepton schematics

[karl]

Felix:
> On Wed, Mar 30, 2022 at 10:12:10PM +0200, karl@aspodata.se wrote:
> > Seems "everything" is a module, and you can just call the top module
> > main if you'd like.
> 
> Not sure what you mean. What is a top module?

https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf
p.129 "6.1 Overview"
 To describe a hierarchy of modules, the user provides textual definitions
 of various modules. Each module definition stands alone; the definitions
 are not nested. Statements within the module definitions create instances
 of other modules, thus describing the hierarchy.

p.131 "6.2.1 Top-level modules and $root"
 Top-level modules are modules that are included in the source text, but do
 not appear in any module instantiation statement, as described in 6.2.2.

So a top level module is a module not referenced by other modules.

> There is only (exactly) one circuit in a gEDA schematic (didn't we agree
> to stick to this?).

Don't remember that, but in a schematic structure, you can choose to
focus on a sub-hier., so there can possible be multiple cirucuits, 
especially if the top sheet is just a collection not connected 
subsheets. You can do that to make it easier to browse through some
possible unrelated projects.
 Also, a top sheet can ref. submodules connected via cables, and when
simulating you might want to simulate them seperately.

But in the end, source symbols in a sch file are not required to be 
interconnected, so there no such thing as one circuite in a geda 
schematic, unless the user imposes such a rule.

> The standard suggests to call it "main", which is as
> close as you get to "objects at top-level". Now you may call it "fred",
> but that won't lead much further.

There is no mention of the name main as a module name in the above pdf.
I'd use the sch file name without the .sch/.sym suffix as module name.

...
> > > >From there, you can think about flattening. Perhaps gnucap-geda does it
> > > "the wrong way", but it will adapt.
> > 
> > >From what I read about verilog-ams, you don't need to flatten the nets,
> > it follows from the structure.
> 
> Not sure what you mean. You can flatten the hierarchy, and there may be
> good reasons you would want that. How does this relate to Verilog-ams?
> 
> It all depends on what you'd like to do. Please expand on that end.

>From what I understand after reading the above pdf, is that you can 
flatten or not flatten. For a .sch to verilog-ams converter, I'd prefer
to keep the structure as it is in the .sch files, that would make it
easier to do backannotations.

Regards,
/Karl Hammar