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[PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree |
Date: |
Sat, 23 Oct 2021 23:47:38 +0200 |
Convert the LDI opcode (Immediate Load) to decodetree. Since it
overlaps with the generic MSA handler, use a decodetree overlap
group.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 8 +++++++-
target/mips/tcg/msa_translate.c | 30 ++++++++++++++++++++++--------
2 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index aa784cf12a9..86aa66f05b9 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -14,10 +14,12 @@
&r rs rt rd sa
&msa_bz df wt sa
+&msa_ldst df wd ws sa
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldst ws=0
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
@@ -27,4 +29,8 @@ BNZ_V 010001 01111 ..... ................
@bz_v
BZ 010001 110 .. ..... ................ @bz
BNZ 010001 111 .. ..... ................ @bz
-MSA 011110 --------------------------
+{
+ LDI 011110 110 .. .......... ..... 000111 @ldi
+
+ MSA 011110 --------------------------
+}
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index c2a48aecc46..3b0dfcca69d 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -70,7 +70,6 @@ enum {
OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07,
OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06,
OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07,
- OPC_LDI_df = (0x6 << 23) | OPC_MSA_I5_07,
/* I8 instruction */
OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
@@ -525,13 +524,6 @@ static void gen_msa_i5(DisasContext *ctx)
case OPC_CLEI_U_df:
gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
break;
- case OPC_LDI_df:
- {
- int32_t s10 = sextract32(ctx->opcode, 11, 10);
- tcg_gen_movi_i32(timm, s10);
- gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
- }
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -544,6 +536,28 @@ static void gen_msa_i5(DisasContext *ctx)
tcg_temp_free_i32(timm);
}
+static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
+{
+ TCGv_i32 tdf;
+ TCGv_i32 twd;
+ TCGv_i32 timm;
+
+ if (!check_msa_access(ctx)) {
+ return false;
+ }
+
+ tdf = tcg_constant_i32(a->df);
+ twd = tcg_const_i32(a->wd);
+ timm = tcg_const_i32(a->sa);
+
+ gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
+
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(timm);
+
+ return true;
+}
+
static void gen_msa_bit(DisasContext *ctx)
{
#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
--
2.31.1
- Re: [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path, (continued)
- [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 05/33] target/mips: Have check_msa_access() return a boolean, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 10/33] target/mips: Extract df_extract() helper, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/23