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[PULL 11/52] tcg: Split out tcg-target-reg-bits.h
From: |
Richard Henderson |
Subject: |
[PULL 11/52] tcg: Split out tcg-target-reg-bits.h |
Date: |
Mon, 5 Jun 2023 13:15:07 -0700 |
Often, the only thing we need to know about the TCG host
is the register size.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 12 +-----------
tcg/aarch64/tcg-target-reg-bits.h | 12 ++++++++++++
tcg/arm/tcg-target-reg-bits.h | 12 ++++++++++++
tcg/i386/tcg-target-reg-bits.h | 16 ++++++++++++++++
tcg/i386/tcg-target.h | 2 --
tcg/loongarch64/tcg-target-reg-bits.h | 21 +++++++++++++++++++++
tcg/loongarch64/tcg-target.h | 11 -----------
tcg/mips/tcg-target-reg-bits.h | 18 ++++++++++++++++++
tcg/mips/tcg-target.h | 8 --------
tcg/ppc/tcg-target-reg-bits.h | 16 ++++++++++++++++
tcg/ppc/tcg-target.h | 5 -----
tcg/riscv/tcg-target-reg-bits.h | 19 +++++++++++++++++++
tcg/riscv/tcg-target.h | 9 ---------
tcg/s390x/tcg-target-reg-bits.h | 17 +++++++++++++++++
tcg/sparc64/tcg-target-reg-bits.h | 12 ++++++++++++
tcg/tci/tcg-target-reg-bits.h | 18 ++++++++++++++++++
tcg/tci/tcg-target.h | 8 --------
tcg/s390x/tcg-target.c.inc | 5 -----
18 files changed, 162 insertions(+), 59 deletions(-)
create mode 100644 tcg/aarch64/tcg-target-reg-bits.h
create mode 100644 tcg/arm/tcg-target-reg-bits.h
create mode 100644 tcg/i386/tcg-target-reg-bits.h
create mode 100644 tcg/loongarch64/tcg-target-reg-bits.h
create mode 100644 tcg/mips/tcg-target-reg-bits.h
create mode 100644 tcg/ppc/tcg-target-reg-bits.h
create mode 100644 tcg/riscv/tcg-target-reg-bits.h
create mode 100644 tcg/s390x/tcg-target-reg-bits.h
create mode 100644 tcg/sparc64/tcg-target-reg-bits.h
create mode 100644 tcg/tci/tcg-target-reg-bits.h
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 54f260a66b..5fe90cbb42 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -32,6 +32,7 @@
#include "qemu/plugin.h"
#include "qemu/queue.h"
#include "tcg/tcg-mo.h"
+#include "tcg-target-reg-bits.h"
#include "tcg-target.h"
#include "tcg/tcg-cond.h"
#include "tcg/debug-assert.h"
@@ -44,17 +45,6 @@
#define CPU_TEMP_BUF_NLONGS 128
#define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long))
-/* Default target word size to pointer size. */
-#ifndef TCG_TARGET_REG_BITS
-# if UINTPTR_MAX == UINT32_MAX
-# define TCG_TARGET_REG_BITS 32
-# elif UINTPTR_MAX == UINT64_MAX
-# define TCG_TARGET_REG_BITS 64
-# else
-# error Unknown pointer size for tcg target
-# endif
-#endif
-
#if TCG_TARGET_REG_BITS == 32
typedef int32_t tcg_target_long;
typedef uint32_t tcg_target_ulong;
diff --git a/tcg/aarch64/tcg-target-reg-bits.h
b/tcg/aarch64/tcg-target-reg-bits.h
new file mode 100644
index 0000000000..3b57a1aafb
--- /dev/null
+++ b/tcg/aarch64/tcg-target-reg-bits.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Define target-specific register size
+ * Copyright (c) 2023 Linaro
+ */
+
+#ifndef TCG_TARGET_REG_BITS_H
+#define TCG_TARGET_REG_BITS_H
+
+#define TCG_TARGET_REG_BITS 64
+
+#endif
diff --git a/tcg/arm/tcg-target-reg-bits.h b/tcg/arm/tcg-target-reg-bits.h
new file mode 100644
index 0000000000..23b7730a8d
--- /dev/null
+++ b/tcg/arm/tcg-target-reg-bits.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define target-specific register size
+ * Copyright (c) 2023 Linaro
+ */
+
+#ifndef TCG_TARGET_REG_BITS_H
+#define TCG_TARGET_REG_BITS_H
+
+#define TCG_TARGET_REG_BITS 32
+
+#endif
diff --git a/tcg/i386/tcg-target-reg-bits.h b/tcg/i386/tcg-target-reg-bits.h
new file mode 100644
index 0000000000..aa386050eb
--- /dev/null
+++ b/tcg/i386/tcg-target-reg-bits.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define target-specific register size
+ * Copyright (c) 2008 Fabrice Bellard
+ */
+
+#ifndef TCG_TARGET_REG_BITS_H
+#define TCG_TARGET_REG_BITS_H
+
+#ifdef __x86_64__
+# define TCG_TARGET_REG_BITS 64
+#else
+# define TCG_TARGET_REG_BITS 32
+#endif
+
+#endif
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 1468f8ef25..2a2e3fffa8 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -30,11 +30,9 @@
#define TCG_TARGET_INSN_UNIT_SIZE 1
#ifdef __x86_64__
-# define TCG_TARGET_REG_BITS 64
# define TCG_TARGET_NB_REGS 32
# define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB)
#else
-# define TCG_TARGET_REG_BITS 32
# define TCG_TARGET_NB_REGS 24
# define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX
#endif
diff --git a/tcg/loongarch64/tcg-target-reg-bits.h
b/tcg/loongarch64/tcg-target-reg-bits.h
new file mode 100644
index 0000000000..51373ad70a
--- /dev/null
+++ b/tcg/loongarch64/tcg-target-reg-bits.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define target-specific register size
+ * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
+ */
+
+#ifndef TCG_TARGET_REG_BITS_H
+#define TCG_TARGET_REG_BITS_H
+
+/*
+ * Loongson removed the (incomplete) 32-bit support from kernel and toolchain
+ * for the initial upstreaming of this architecture, so don't bother and just
+ * support the LP64* ABI for now.
+ */
+#if defined(__loongarch64)
+# define TCG_TARGET_REG_BITS 64
+#else
+# error unsupported LoongArch register size
+#endif
+
+#endif
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 482901ac15..26f1aab780 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -29,17 +29,6 @@
#ifndef LOONGARCH_TCG_TARGET_H
#define LOONGARCH_TCG_TARGET_H
-/*
- * Loongson removed the (incomplete) 32-bit support from kernel and toolchain
- * for the initial upstreaming of this architecture, so don't bother and just
- * support the LP64* ABI for now.
- */
-#if defined(__loongarch64)
-# define TCG_TARGET_REG_BITS 64
-#else
-# error unsupported LoongArch register size
-#endif
-
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_NB_REGS 32
diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h
new file mode 100644
index 0000000000..56fe0a725e
--- /dev/null
+++ b/tcg/mips/tcg-target-reg-bits.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define target-specific register size
+ * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
+ */
+
+#ifndef TCG_TARGET_REG_BITS_H
+#define TCG_TARGET_REG_BITS_H
+
+#if _MIPS_SIM == _ABIO32
+# define TCG_TARGET_REG_BITS 32
+#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
+# define TCG_TARGET_REG_BITS 64
+#else
+# error "Unknown ABI"
+#endif
+
+#endif
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index e4806f6ff5..dd2efa795c 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -27,14 +27,6 @@
#ifndef MIPS_TCG_TARGET_H
#define MIPS_TCG_TARGET_H
-#if _MIPS_SIM == _ABIO32
-# define TCG_TARGET_REG_BITS 32
-#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
-# define TCG_TARGET_REG_BITS 64
-#else
-# error "Unknown ABI"
-#endif
-
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_NB_REGS 32
diff --git a/tcg/ppc/tcg-target-reg-bits.h b/tcg/ppc/tcg-target-reg-bits.h
new file mode 100644
index 0000000000..0efa80e7e0
--- /dev/null
+++ b/tcg/ppc/tcg-target-reg-bits.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define target-specific register size
+ * Copyright (c) 2008 Fabrice Bellard
+ */
+
+#ifndef TCG_TARGET_REG_BITS_H
+#define TCG_TARGET_REG_BITS_H
+
+#ifdef _ARCH_PPC64
+# define TCG_TARGET_REG_BITS 64
+#else
+# define TCG_TARGET_REG_BITS 32
+#endif
+
+#endif
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 40f20b0c1a..c7552b6391 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -25,11 +25,6 @@
#ifndef PPC_TCG_TARGET_H
#define PPC_TCG_TARGET_H
-#ifdef _ARCH_PPC64
-# define TCG_TARGET_REG_BITS 64
-#else
-# define TCG_TARGET_REG_BITS 32
-#endif
#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
#define TCG_TARGET_NB_REGS 64
diff --git a/tcg/riscv/tcg-target-reg-bits.h b/tcg/riscv/tcg-target-reg-bits.h
new file mode 100644
index 0000000000..761ca0d774
--- /dev/null
+++ b/tcg/riscv/tcg-target-reg-bits.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define target-specific register size
+ * Copyright (c) 2018 SiFive, Inc
+ */
+
+#ifndef TCG_TARGET_REG_BITS_H
+#define TCG_TARGET_REG_BITS_H
+
+/*
+ * We don't support oversize guests.
+ * Since we will only build tcg once, this in turn requires a 64-bit host.
+ */
+#if __riscv_xlen != 64
+#error "unsupported code generation mode"
+#endif
+#define TCG_TARGET_REG_BITS 64
+
+#endif
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 54fdff0caa..e1d8110ee4 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -25,15 +25,6 @@
#ifndef RISCV_TCG_TARGET_H
#define RISCV_TCG_TARGET_H
-/*
- * We don't support oversize guests.
- * Since we will only build tcg once, this in turn requires a 64-bit host.
- */
-#if __riscv_xlen != 64
-#error "unsupported code generation mode"
-#endif
-#define TCG_TARGET_REG_BITS 64
-
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_NB_REGS 32
#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
diff --git a/tcg/s390x/tcg-target-reg-bits.h b/tcg/s390x/tcg-target-reg-bits.h
new file mode 100644
index 0000000000..b01414e09d
--- /dev/null
+++ b/tcg/s390x/tcg-target-reg-bits.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define target-specific register size
+ * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
+ */
+
+#ifndef TCG_TARGET_REG_BITS_H
+#define TCG_TARGET_REG_BITS_H
+
+/* We only support generating code for 64-bit mode. */
+#if UINTPTR_MAX == UINT64_MAX
+# define TCG_TARGET_REG_BITS 64
+#else
+# error "unsupported code generation mode"
+#endif
+
+#endif
diff --git a/tcg/sparc64/tcg-target-reg-bits.h
b/tcg/sparc64/tcg-target-reg-bits.h
new file mode 100644
index 0000000000..34a6711013
--- /dev/null
+++ b/tcg/sparc64/tcg-target-reg-bits.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define target-specific register size
+ * Copyright (c) 2023 Linaro
+ */
+
+#ifndef TCG_TARGET_REG_BITS_H
+#define TCG_TARGET_REG_BITS_H
+
+#define TCG_TARGET_REG_BITS 64
+
+#endif
diff --git a/tcg/tci/tcg-target-reg-bits.h b/tcg/tci/tcg-target-reg-bits.h
new file mode 100644
index 0000000000..dcb1a203f8
--- /dev/null
+++ b/tcg/tci/tcg-target-reg-bits.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define target-specific register size
+ * Copyright (c) 2009, 2011 Stefan Weil
+ */
+
+#ifndef TCG_TARGET_REG_BITS_H
+#define TCG_TARGET_REG_BITS_H
+
+#if UINTPTR_MAX == UINT32_MAX
+# define TCG_TARGET_REG_BITS 32
+#elif UINTPTR_MAX == UINT64_MAX
+# define TCG_TARGET_REG_BITS 64
+#else
+# error Unknown pointer size for tci target
+#endif
+
+#endif
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 60a6ed65ce..37ee10c959 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -44,14 +44,6 @@
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
-#if UINTPTR_MAX == UINT32_MAX
-# define TCG_TARGET_REG_BITS 32
-#elif UINTPTR_MAX == UINT64_MAX
-# define TCG_TARGET_REG_BITS 64
-#else
-# error Unknown pointer size for tci target
-#endif
-
/* Optional instructions. */
#define TCG_TARGET_HAS_bswap16_i32 1
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index aeddebbb5c..a878acd8ca 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -24,11 +24,6 @@
* THE SOFTWARE.
*/
-/* We only support generating code for 64-bit mode. */
-#if TCG_TARGET_REG_BITS != 64
-#error "unsupported code generation mode"
-#endif
-
#include "../tcg-ldst.c.inc"
#include "../tcg-pool.c.inc"
#include "elf.h"
--
2.34.1
- [PULL 00/52] tcg patch queue, Richard Henderson, 2023/06/05
- [PULL 01/52] tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/06/05
- [PULL 03/52] tcg/s390x: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/06/05
- [PULL 04/52] tcg/sparc64: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/06/05
- [PULL 05/52] tcg: Move TCG_TYPE_TL from tcg.h to tcg-op.h, Richard Henderson, 2023/06/05
- [PULL 06/52] tcg: Widen CPUTLBEntry comparators to 64-bits, Richard Henderson, 2023/06/05
- [PULL 08/52] target/avr: Add missing includes of qemu/error-report.h, Richard Henderson, 2023/06/05
- [PULL 09/52] target/*: Add missing includes of tcg/debug-assert.h, Richard Henderson, 2023/06/05
- [PULL 07/52] tcg: Add tlb_fast_offset to TCGContext, Richard Henderson, 2023/06/05
- [PULL 11/52] tcg: Split out tcg-target-reg-bits.h,
Richard Henderson <=
- [PULL 13/52] tcg: Split out tcg/oversized-guest.h, Richard Henderson, 2023/06/05
- [PULL 02/52] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/06/05
- [PULL 10/52] *: Add missing includes of tcg/tcg.h, Richard Henderson, 2023/06/05
- [PULL 12/52] target/arm: Fix test of TCG_OVERSIZED_GUEST, Richard Henderson, 2023/06/05
- [PULL 14/52] tcg: Move TCGv, dup_const_tl definitions to tcg-op.h, Richard Henderson, 2023/06/05
- [PULL 18/52] tcg: Remove outdated comments in helper-head.h, Richard Henderson, 2023/06/05
- [PULL 17/52] target/hexagon: Include helper-gen.h where needed, Richard Henderson, 2023/06/05
- [PULL 16/52] target/arm: Include helper-gen.h in translator.h, Richard Henderson, 2023/06/05
- [PULL 19/52] tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h, Richard Henderson, 2023/06/05
- [PULL 21/52] tcg: Move temp_idx and tcgv_i32_temp debug out of line, Richard Henderson, 2023/06/05